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m68hc05 microcontrollers freescale.com MC68HC05C9E advance information data sheet MC68HC05C9E rev. 0.1 9/2005 this document contains certain information on a new product.spec ifications and information herein are subject to change without notice.
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MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. ? freescale semiconductor, inc., 2005. all rights reserved. MC68HC05C9E advance information data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.freescale.com/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) september 2005 0.1 updated to meet freescale identity guidelines. throughout
revision history MC68HC05C9E advance information data sheet, rev. 0.1 4 freescale semiconductor
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 chapter 2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chapter 3 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 chapter 4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 chapter 5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 chapter 6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 chapter 7 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 chapter 8 capture/compare timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 chapter 9 serial communications interf ace (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 chapter 10 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 chapter 11 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 chapter 12 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 chapter 13 mechanical specificati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 chapter 14 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 appendix a self-check mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 appendix b m68hc05cx family feature comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . 103
list of chapters MC68HC05C9E advance information data sheet, rev. 0.1 6 freescale semiconductor
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 software-programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5 functional pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.2 irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.3 osc1 andosc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.5 tcap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.6 tcmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.7 pa0?pa7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.8 pb0?pb7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.9 pc0?pc7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.10 pd0?pd5 and pd7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 chapter 2 memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 rom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 rom security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 chapter 3 central processor unit (cpu) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.1 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.2 index register (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.3 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.5 condition code register (ccr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 chapter 4 interrupts 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 non-maskable software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 external interrupt (irq or port b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
table of contents MC68HC05C9E advance information data sheet, rev. 0.1 8 freescale semiconductor 4.4 timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5 sci interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.6 spi interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 chapter 5 resets 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 reset pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4.1 cop reset register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4.2 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5 cop during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6 cop during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.7 clock monitor reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 chapter 6 low-power modes 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 chapter 7 input/output ports 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 port c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.5 port d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 chapter 8 capture/compare timer 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.2.1 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.2.2 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.3 timer i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.3.1 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3.2 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.3.3 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3.4 alternate timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3.5 input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.3.6 output compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.4 timer during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.5 timer during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
table of contents MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 9 chapter 9 serial communications interface (sci) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.3 sci receiver features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.4 sci transmitter features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.6 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.7 receiver wakeup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.7.1 idle line wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.7.2 address mark wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.8 receive data in (rdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.9 start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.10 transmit data out (tdo). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.11 sci i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.11.1 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.11.2 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.11.3 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.11.4 sci status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.11.5 baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 chapter 10 serial peripheral interface (spi) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.3 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.3.1 master in/slave out (miso). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.3.2 master out/slave in (mosi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.3.3 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.3.4 slave select (ss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.5 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.5.1 serial peripheral control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.5.2 serial peripheral status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.5.3 serial peripheral data i/o register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 chapter 11 instruction set 11.1 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.1.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.1.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.1.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.1.7 indexed, 16-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.1.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
table of contents MC68HC05C9E advance information data sheet, rev. 0.1 10 freescale semiconductor 11.2 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.2.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.2.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.2.3 jump/branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.2.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.3 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.4 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 chapter 12 electrical specifications 12.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.2 operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.4 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.6 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.7 serial peripheral interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 chapter 13 mechanical specifications 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.2 40-pin plastic dual in-line (dip) package (case 711-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.3 44-lead quad flat pack (qfp) (case 824a-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 chapter 14 ordering information 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 appendix a self-check mode a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 a.2 self-check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 a.3 self-check results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 appendix b m68hc05cx family feature comparisons
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 11 chapter 1 general description 1.1 introduction the MC68HC05C9E hcmos (high-density complementar y metal-oxide semiconductor) microcontroller is a member of the m68hc05 family. the mc68hc05c9 e memory map consists of 15,936 bytes of user rom and 352 bytes of ram. the MC68HC05C9E includes a serial communications interface, a serial peripheral interface, and a 16-bit capture/compare timer. 1.2 features features of the MC68HC05C9E include: m68hc05 cpu mask programmable interrupt capability on port b software programmable external interrupt sensitivity 15,936 bytes of read-only memory (rom) 352 bytes of random-access memory (ram) memory mapped input/output (i/o) 31 bidirectional i/o lines with high current sink and source on pc7 asynchronous serial communications interface (sci) synchronous serial peripheral interface (spi) 16-bit capture/compare timer computer operating properly (c op) watchdog timer and clock monitor power-saving wait and stop modes on-chip crystal oscillator connections single 4.5 volts to 5.5 volts power supply requirement rom contents security (1) feature available packages: ? 40-pin dual in-line (dip) ? 44-pin quad flat pack (qfp) 1.3 mask options eight mask options are available to select external interrupt capability (including an internal pullup device) on each of the port b pins. 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the rom difficult for unauthorized users.
general description MC68HC05C9E advance information data sheet, rev. 0.1 12 freescale semiconductor figure 1-1. block diagram 0 000 001 1 cpu control arithmetic logic unit accumulator index register stack pointer program counter m68hc05 mcu reset condition code register 111hi ncz data direction register a port a pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 cop internal oscillator divide by two capture/ irq v dd v ss osc1 osc2 user ram ? 352 bytes reset data direction register b port b pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 data direction register c port c user rom ? 15,936 bytes pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 compare timer tcmp tcap watchdog cpu clock power internal clock spi generator baud rate sci ss sck mosi miso tdo rdi data direction register d port d pd7 pd5/ss pd4/sck pd3/mosi pd2/miso pd1/tdo pd0/rdi divide by four timer clock self-check rom ? 239 bytes
software-programmable options MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 13 1.4 software-programmable options the option register (or), shown in figure 1-2 , contains the programmable bits for these options: map two different areas of memory between ram and rom, one of 48 bytes and one of 128 bytes edge-triggered only or edge- and level-triggered external interrupt (irq pin and any port b pin configured for interrupt) this register must be written to by user software during operation of the microcontroller. ram0 ? random-access memory control bit 0 this read/write bit selects between ram or rom in location $0020 to $004f. this bit can be read or written at any time. 1 = ram selected 0 = rom selected ram1? random-access memory control bit 1 this read/write bit selects between ram or rom in location $0100 to $017f. this bit can be read or written at any time. 1 = ram selected 0 = eprom selected irq ? interrupt request bit this bit selects between an edge-triggered only or edge- and level- triggered external interrupt. this bit is set by reset, but can be cleared by so ftware. this bit can be written only once. 1 = edge and level interrupt option selected 0 = edge-only interrupt option selected 1.5 functional pin descriptions figure 1-3 and figure 1-4 show the pin assignments for the avai lable packages. a functional description of the pins follows. note a line over a signal name indicates an active low signal. for example, reset is active high and reset is active low. address: $3fdf bit 7654321bit 0 read: ram0 ram1 0000 irq 0 write: reset:00000010 = unimplemented figure 1-2. option register
general description MC68HC05C9E advance information data sheet, rev. 0.1 14 freescale semiconductor figure 1-3. 40-pin pdip pin assignments 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pd0/rdi pd1/tdo pd2/miso pd3/mosi pd4/sck pd5/ss tcmp pd7 tcap osc2 osc1 v dd v ss pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 n/c irq reset
functional pin descriptions MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 15 figure 1-4. 44-pin qfp pin assignments 1.5.1 v dd and v ss power is supplied to the mc u using these two pins. v dd is the positive supply and v ss is ground. 1.5.2 irq this interrupt pin has an option that provides two different choices of interrupt triggering sensitivity. the irq pin contains an internal schmi tt trigger as part of its input to improve noise immunity. refer to chapter 4 interrupts for more detail. 1.5.3 osc1 andosc2 these pins provide control input for an on-chip clo ck oscillator circuit. a crystal or ceramic resonator connected to these pins provides a system clock. the internal frequency is one-half the crystal frequency. 1.5.4 reset as an input pin, this active low reset pin is used to reset the mcu to a known startup state by pulling reset low. as an output pin, the reset pin indicates that an internal mcu reset has occurred. the reset pin contains an internal schmitt trigger as part of its input to improve noise immunity. refer to chapter 5 resets for more detail. 33 32 31 30 29 28 27 26 25 24 23 pc3 pc2 pc1 pc0 pd0/rdi pd1/tdo pd2/miso pd3/mosi pd4/sck pd5/ss tcmp 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 44 43 42 41 40 38 37 36 35 34 pd7 pc4 pc5 pc6 pc7 v ss n/c pb7 pb6 pb5 pb4 tcap osc2 osc1 v dd n/c n/c reset irq n/c pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb0 pb1 pb2 pb3 39 n/c
general description MC68HC05C9E advance information data sheet, rev. 0.1 16 freescale semiconductor 1.5.5 tcap this pin controls the input capture feature for the on-chip programmable timer. the tcap pin contains an internal schmitt trigger as part of its input to improve noise immunity. refer to chapter 8 capture/compare timer for more detail. 1.5.6 tcmp the tcmp pin provides an output for the output com pare feature of the on-chip programmable timer. refer to chapter 8 capture/compare timer for more detail. 1.5.7 pa0?pa7 these eight i/o lines comprise port a. the state of each pin is software programmable and all port a pins are configured as inputs during reset. refer to chapter 7 input/output ports for more detail. 1.5.8 pb0?pb7 these eight i/o lines comprise port b. the state of each pin is software programmable and all port b pins are configured as inputs during reset. port b has mask option register enabled pullup devices and interrupt capability selectable for any pin. refer to chapter 7 input/output ports for more detail. 1.5.9 pc0?pc7 these eight i/o lines comprise port c. the state of each pin is software programmable and all port c pins are configured as inputs during reset. pc7 has high current sink and source capability. refer to chapter 7 input/output ports for more detail. 1.5.10 pd0?pd5 and pd7 these seven i/o lines comprise port d. the state of each pin is software programmable and all port d pins are configured as inputs during reset. refer to chapter 7 input/output ports for more detail.
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 17 chapter 2 memory 2.1 introduction the microcontroller unit (mcu) has a 16-kbyte memory map. the memory map consists of: input/output (i/o), control, and status registers user random-access memory (ram) user read-only memory (rom) self-check rom reset and interrupt vectors see figure 2-1 and figure 2-2 . two control bits in the option register ($3fdf) allow the user to switch between ram and rom at any time in two special areas of the memory m ap, $0020?$004f (48 bytes) and $0100?$017f (128 bytes). 2.2 ram the main user ram consists of 176 bytes at $005 0?$00ff. this ram area is always present in the memory map and includes a 64-byte stack area. the stack pointer can access 64 bytes of ram in the range $00ff down to $00c0. note using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. two additional ram areas are avai lable at $0020?$004f (48 bytes) and $0100?$017f (128 bytes) (see figure 2-1 and figure 2-2 .) these may be accessed at any time by setting the ram0 and ram1 bits, respectively, in the option register. refer to 1.4 software-programmable options for additional information. 2.3 rom the user rom consists of 48 bytes of page zero rom from $0020 to $004f, 15,872 bytes of rom from $0100 to $3eff, and 16 bytes of user vectors from $3ff0 to $3fff. 2.4 rom security a security feature has been incorporated into the mc 68hc05c9e to help prevent external access to the contents of the rom in any mode of operation.
memory MC68HC05C9E advance information data sheet, rev. 0.1 18 freescale semiconductor figure 2-1. memory map port a data register port b data register port c data register port d data register port a data direction register port b data direction register port c data direction register port d data direction register unused unused spi control register spi status register spi data register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register input capture register (high) spi vector (high) spi vector (low) sci vector (high) sci vector (low) timer vector (high) timer vector (low) irq vector (high) irq vector (low) swi vector (high) swi vector (low) reset vector (high byte) reset vector (low byte) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0012 $0011 $0013 $0019 $001a $001b $001c $3ff4 $3ff3 $3ff5 $3ff6 $3ff7 $3ff8 i/o registers 32 bytes $0000 $001f $0020 $004f $0050 ram 176 bytes $00ff $0100 user rom 15,744 bytes $017f $0180 user rom vectors $3fff 16 bytes $0014 input capture register (low) output compare register (high) output compare register (low) timer counter register (high) $3ff9 $3ffb $3ffa $3ffc $3ffd $3ffe $3fff timer counter register (low) $0015 $0016 $0017 $0018 $001d $001e $001f alternate counter register (high) alternate counter register (low) unused cop reset register cop control register unused $3fef $3eff $3f00 stack 64 bytes ram 48 bytes ram0 = 1 user rom 48 bytes ram0 = 0 ram ram1 = 1 user rom ram1 = 0 128 bytes 128 bytes self-check rom and vectors 239 bytes $00bf $00c0 $3ff0 $3ff0 unused (4 bytes) option register $3fdf
i/o registers MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 19 2.5 i/o registers except for the option register, all i/o, control and status registers are located within one 32-byte block in page zero of the address space ($0000?$001f). a summary of these registers is shown in figure 2-2 . more detail about the contents of these registers is given in figure 2-3 . address register name $0000 port a data register $0001 port b data register $0002 port c data register $0003 port d data register $0004 port a data direction register $0005 port b data direction register $0006 port c data direction register $0007 port d data direction register $0008 unused $0009 unused $000a serial peripheral control register $000b serial peripheral status register $000c serial peripheral data register $000d baud rate register $000e serial communications control register 1 $000f serial communicatio ns control register 2 $0010 serial communications status register $0011 serial communications data register $0012 timer control register $0013 timer status register $0014 input capture register high $0015 input capture register low $0016 output compare register high $0017 output compare register low $0018 timer register high $0019 timer register low $001a alternate timer register high $001b alternate timer register low $001c unused $001d cop reset register $001e cop control register $001f reserved figure 2-2. i/o register summary
memory MC68HC05C9E advance information data sheet, rev. 0.1 20 freescale semiconductor addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (porta) see page 37. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset $0001 port b data register (portb) see page 38. read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset $0002 port c data register (portc) see page 38. read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset $0003 port d data register (portd) see page 38. read: pd7 pd5 pd4 pd3 pd2 pd1 pd0 write: reset: unaffected by reset $0004 port a data direction register (ddra) see page 37. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0005 port b data direction register (ddrb) see page 38. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0006 port c data direction register (ddrc) see page 38. read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 0 0 0 0 0 0 0 0 $0007 port d data direction register (ddrd) see page 38. read: ddrc7 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 0 0 0 0 0 0 0 0 $0008 unimplemented $0009 unimplemented $000a spi control register (spcr) see page 64. read: spie spe dwom mstr cpol cpha spr1 spr0 write: reset: 0 0 0 0 0 1 u u $000b spi status register (spsr) see page 66. read: spif wcol 0 modf 0 0 0 0 write: reset: 0 0 0 0 0 0 0 0 $000c spi data register (spdr) see page 67. read: spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 write: reset: unaffected by reset = unimplemented r = reserved u = unaffected figure 2-3. input/output registers (sheet 1 of 3)
i/o registers MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 21 $000d sci baud rate register baud see page 59. read: scp1 scp0 scr2 scr1 scr0 write: reset: ? ? 0 0 ? u u u $000e sci control register 1 (sccr1) see page 55. read: r8 t8 m wake write: reset: u u 0 u u 0 0 0 $000f sci control register 2 (sccr2) see page 56. read: tie tcie rie ilie te re rmw sbk write: reset: 0 0 0 0 0 0 0 0 $0010 sci status register (scsr) see page 57. read: tdre tc rdrf idle or nf fe write: reset: 1 1 0 0 0 0 0 ? $0011 sci data register (scdr) see page 55. read: scd7 sdc6 scd5 scd4 scd3 scd2 scd1 scd0 write: reset: unaffected by reset $0012 timer control register (tcr) see page 43. read: icie ocie toie 000 iedg olvl write: reset: 0 0 0 0 0 0 u 0 $0013 timer status register (tsr) see page 44. read: icf ocf tof 0 0 0 0 0 write: reset: u u u 0 0 0 0 0 $0014 input capture register high (icrh) see page 46. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0015 input capture register low (icrl) see page 46. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0016 output compare register high (ocrh) see page 46. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0017 output compare register low (ocrl) see page 46. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0018 timer register high (trh) see page 45. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 2-3. input/output registers (sheet 2 of 3)
memory MC68HC05C9E advance information data sheet, rev. 0.1 22 freescale semiconductor $0019 timer register low (trl) see page 45. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 0 0 $001a alternate timer register high (atrh) see page 45. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $001b alternate timer register low (atrl) see page 45. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 0 0 $001c unimplemented $001d cop reset register (coprst) see page 31. read: write: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset: 0 0 0 0 0 0 0 0 $001e cop control register (copcr) see page 32. read: 0 0 0 copf cme cope cm1 cm0 write: reset: 0 0 0 u 0 0 0 0 $001d unimplemented $001e unimplemented $001f reserved r r r r r r r r addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 2-3. input/output registers (sheet 3 of 3)
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 23 chapter 3 central processor unit (cpu) 3.1 introduction this section contains information describing the ba sic programmer?s model and the registers contained in the central processor unit (cpu). 3.2 cpu registers the microcontroller unit (mcu) contains five regi sters as shown in the programming model of figure 3-1 . the interrupt stacking order is shown in figure 3-2 . figure 3-1. programming model figure 3-2. interrupt stacking order a 70 x 70 hinzc ccr 11 sp 7 0 pc 13 0 accumulator index register program counter stack pointer condition code register 0 13 0 0 0 0 0 index register pcl accumulator condition code register pch 111 70 stack i n t e r r u p t decreasing unstack r e t u r n increasing memory addresses memory addresses
central processor unit (cpu) MC68HC05C9E advance information data sheet, rev. 0.1 24 freescale semiconductor 3.2.1 accumulator (a) the accumulator is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.2.2 index register (x) the index register is an 8-bit register used for the indexed addressing value to create an effective address. the index register may also be used as a temporary storage area. 3.2.3 program counter (pc) the program counter is a 14-bit register that c ontains the address of the next byte to be fetched. 3.2.4 stack pointer (sp) the stack pointer contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $0ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the eight most significant bits are permanently set to 00000011. these eight bits are appended to the six least significant register bi ts to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. 3.2.5 condition code register (ccr) the ccr is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. these bits can be individually tested by a program, and specific actions can be taken as a result of their state. each bit is explained here. half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. interrupt (i) when this bit is set, the timer, serial communications interface (sci), serial peripheral interface (spi), and external interrupt are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was 0. carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is al so affected during bit test and branch instructions and during shifts and rotates.
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 25 chapter 4 interrupts 4.1 introduction the MC68HC05C9E microcontroller unit (mcu) can be interrupted by five different sources: four maskable hardware interrupts, and one non-maskable software interrupt: external signal on the irq pin or port b pins 16-bit programmable timer serial communications interface (sci) serial peripheral interface (spi) software interrupt instruction (swi) interrupts cause the processor to save register content s on the stack and to set the interrupt mask (i bit) to prevent additional interrupts. the return from interrupt (rti) instruction causes the register contents to be recovered from the stack and normal processing to resume. unlike reset, hardware interrupts do not cause the cu rrent instruction executi on to be halted, but are considered pending until the curr ent instruction is complete. note the current instruction is the one already fetched and being operated on. when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (ccr i bit clear) and if th e corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; othe rwise, the next instruction is fetched and executed. if an external interrupt and a timer, sci, or spi interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. the swi is executed the same as any other instruction, regardless of the i-bit state. table 4-1 shows the relative priority of all the possible interrupt sources. figure 4-1 shows the interrupt processing flow. 4.2 non-maskable software interrupt (swi) the swi is an executable instruction and a non-maskabl e interrupt. it is executed regardless of the state of the i bit in the ccr. if the i bit is 0 (interr upts enabled), swi executes after interrupts which were pending when the swi was fetched, but before interrupts generated after the swi was fetched. the interrupt service routine address is specified by the contents of memory locations $3ffc and $3ffd.
interrupts MC68HC05C9E advance information data sheet, rev. 0.1 26 freescale semiconductor 4.3 external interrupt (irq or port b) if the interrupt mask bit (i bit) of the ccr is set, a ll maskable interrupts (internal and external) are disabled. clearing the i bit enables interrupts. the interrupt request is latched immediately following the falling edge of irq . it is then synchronized interna lly and serviced as specified by the contents of $3ffa and $3ffb. when any of the port b pullups are enabled, each pin becomes an additional external interrupt source which is executed identically to the irq pin. port b interrupts follow the same edge/edge-level selection as the irq pin. the branch instructions bil and bih also respond to the port b interrupts in the same way as the irq pin. see 7.3 port b . either a level-sensitive and edge-sensitive trigger or an edge-sensitive-only trigger operation is selectable. the sensitivity is software-controlled by the irq bit in the option register ($3fdf). note the internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse can be latched and serviced as soon as the i bit is cleared. table 4-1. vector addresses for interrupts and resets function source local mask global mask priority (1 = highest) vector address reset power-on reset none none 1 $3ffe?$3fff reset pin cop watchdog software interrupt (swi) user code none none same priority as instruction $3ffc?$3ffd external interrupt irq pin none i bit 2 $3ffa?$3ffb port b pins timer interrupts icf bit icie bit i bit 3 $3ff8?$3ff9 ocf bit ocie bit tof bit toie bit sci interrupts tdre bit tcie bit i bit 4 $3ff6?$3ff7 tc bit rdrf bit rie bit or bit idle bit ilie bit spi interrupts spif bit spie bit i bit 5 $3ff4?$3ff5 modf bit
timer interrupt MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 27 4.4 timer interrupt three different timer interrupt flags cause a time r interrupt whenever they are set and enabled. the interrupt flags are in the timer status register (tsr), and the enable bits are in the timer control register (tcr). any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3ff8 and $3ff9. 4.5 sci interrupt five different sci interrupt flags cause an sci interrupt whenever they are set and enabled. the interrupt flags are in the sci status register (scsr), and the e nable bits are in the sci control register 2 (sccr2). any of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory locations $3ff6 and $3ff7. 4.6 spi interrupt two different spi interrupt flags cause an spi interrupt whenever they are set and enabled. the interrupt flags are in the spi status register (spsr), and the enable bits are in the spi control register (spcr). either of these interrupts will vector to the same inte rrupt service routine, located at the address specified by the contents of memory locations $3ff4 and $3ff5.
interrupts MC68HC05C9E advance information data sheet, rev. 0.1 28 freescale semiconductor figure 4-1. interrupt flowchart fetch next instruction swi instruction ? rti instruction ? execute restore registers from stack: ccr, a, x, pc n y n y instruction stack pc, x, a, ccr set i bit in cc register load pc from: swi: $3ffc?$3ffd irq : $3ffa?$3ffb timer: $3ff8?$3ff9 sci: $3ff6?$3ff7 spi: $3ff4?$3ff5 internal spi interrupt internal sci interrupt y y y y n n n n n internal timer interrupt clear irq request latch irq or port b external interrupt i bit in ccr set? from reset y
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 29 chapter 5 resets 5.1 introduction the MC68HC05C9E microcontroller unit (mcu) can be reset four ways: initial power-on reset function active low input to the reset pin computer operating properly (cop) clock monitor a reset immediately stops the operation of the instru ction being executed, initializes some control bits, and loads the program counter with a user-defined reset vector address. figure 5-1 is a block diagram of the reset sources. figure 5-1. reset sources 5.2 power-on reset (por) a power-on reset (por) occurs when a positive transition is detected on v dd . the power-on reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. there is a 4064 internal processor clock cycle (t cyc ) oscillator stabilization delay after the oscillator becomes active. the reset pin will output a logic 0 during the 4064-cycle delay. if the reset pin is low after the end of this 4064-cycle delay, the mcu wi ll remain in the reset condition until reset is driven high externally. v dd reset reset latch power-on reset d internal clock r rst to cpu and subsystems q stop clock monitor cop watchdog
resets MC68HC05C9E advance information data sheet, rev. 0.1 30 freescale semiconductor 5.3 reset pin the mcu is reset when a logic 0 is applied to the reset input for a period of one and one-half machine cycles (t rl ). however, to differentiate between an external reset and an internal reset (generated from the cop or clock monitor), any externally driven reset must be active (logic 0) for at least eight t cyc . figure 5-2. power-on reset and reset 5.4 computer operating properly (cop) reset this device includes a watchdog cop feature which guards against program run-away failures. a timeout of the cop timer generates a cop reset. the cop wa tchdog is a software error detection system that automatically times out and resets the mcu if not cleared periodically by a program sequence. the cop is controlled with two registers, one to reset the cop timer and the other to enable and control cop and clock monitor functions. figure 5-3 shows a block diagram of the cop. reset osc1 (2) internal clock (1) internal address bus (1) v dd internal data bus (1) t rl new pch new pcl op code op code pch pcl t cyc 4064 t vddr dummy $3fff new pc new pc $3ffe $3ffe $3ffe new pc new pc $3ffe $3fff $3ffe dummy notes: 1. internal timing signal and bus information are not available externally. 2. osc1 line is not meant to represent fr equency. it is meant to represent only time. 3. the next rising edge of the internal processor clock following the rising edge of reset initiates the reset sequence. note 4 4. reset outputs v ol during 4064 power-on reset cycles. note 3 t cyc
computer operating properly (cop) reset MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 31 figure 5-3. cop block diagram 5.4.1 cop reset register the cop reset register (coprst), shown in figure 5-4 , is a write-only register used to reset the cop. the sequence required to reset the cop timer is: write $55 to the cop reset register write $aa to the cop reset register both write operations must occur in the order listed, but any number of instructions may be executed between the two write operations provided that th e cop does not time out between the two writes. the elapsed time between software resets must not be gr eater than the cop timeout period. if the cop should time out, a system reset will occur and the dev ice will be re-initialized in the same fashion as a power-on reset or reset. reading this register does not return valid data. 5.4.2 cop control register the cop control register (copcr), shown in figure 5-5 , performs these functions: enables clock monitor function enables cop function selects timeout duration of cop timer and flags these conditions: cop timeout clock monitor reset address: $001d bit 7654321bit 0 read: write: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset:00000000 = unimplemented figure 5-4. cop reset register (coprst) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 2 2 2 2 2 2 2 13 2 15 2 17 2 19 2 21 coprst cm0 cm1 16-bit timer system internal cpu clock cop
resets MC68HC05C9E advance information data sheet, rev. 0.1 32 freescale semiconductor copf ? computer operating properly flag reading the cop control register clears copf. 1 = cop or clock monitor reset has occurred. 0 = no cop or clock monitor reset has occurred. cme ? clock monitor enable bit this bit is readable any time, but may be written only once. 1 = clock monitor enabled 0 = clock monitor disabled cope ? cop enable bit this bit is readable any time. cope, cm1, and cm0 to gether may be written with a single write, only once, after reset. this bi t is cleared by reset. 1 = cop enabled 0 = cop disabled cm1 ? cop mode bit 1 used in conjunction with cm0 to establish the cop timeout period, this bit is readable any time. cope, cm1, and cm0 together may be written with a single writ e, only once, after reset. this bit is cleared by reset. see table 5-1 for timeout period options. cm0 ? cop mode bit 0 used in conjunction with cm1 to establish the cop timeout period, this bit is readable any time. cope, cm1, and cm0 together may be written with a single writ e, only once, after reset. this bit is cleared by reset. see table 5-1 for timeout period options. bits 7?5 ? not used these bits always read as 0. address: $001e bit 7654321bit 0 read: 0 0 0 copf cme cope cm1 cm0 write: reset:000u0000 = unimplemented u = undetermined figure 5-5. cop control register (copcr) table 5-1. cop timeout period cm1 cm0 f op /2 15 divide by timeout period (f osc = 2.0 mhz) timeout period (f osc = 4.0 mhz) 0 0 1 32.77 ms 16.38 ms 0 1 4 131.07 ms 65.54 ms 1 0 16 524.29 ms 262.14 ms 1 1 64 2.097 s 1.048 s
cop during wait mode MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 33 5.5 cop during wait mode the cop will continue to operate normally during wait mode. the software must pull the device out of wait mode periodically and reset the cop to prevent a system reset. 5.6 cop during stop mode stop mode disables the oscillator circuit and ther eby turns the clock off for the entire device. the cop counter will be reset when stop mode is entered. if a re set is used to exit stop mode, the cop counter will be reset after the 4064 cycles of delay after stop mode. if an irq is used to exit stop mode, the cop counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when control is returned to the program. in the event that an inadvertent stop instruction is executed, the cop will not provide a reset. the clock monitor function provides protection for this situation. 5.7 clock monitor reset the clock monitor circuit can provide a system reset if the clock stops for any reason, including stop mode. when the cme bit in the cop control register is set, the clock monitor detects the absence of the internal bus clock for a certain period of time. the timeou t period is dependent on the processing parameters and varies from 5 s to 100 s, which implies that systems using a bus clock rate of 200 khz or less should not use the clock monitor. if a slow or absent clock is detected, the clock monito r causes a system reset. the reset is issued to the external system via the bidirectional reset pin for four bus cycles if the clock is slow or until the clocks recover in the case where the clocks are absent.
resets MC68HC05C9E advance information data sheet, rev. 0.1 34 freescale semiconductor
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 35 chapter 6 low-power modes 6.1 introduction this section describes the low-power stop and wait modes. 6.2 stop mode the stop instruction places the microcontroller uni t (mcu) in its lowest-power consumption mode. in stop mode, the internal oscillator is turned off, halti ng all internal processing, including timer operation. during stop mode, the tcr bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts. the timer prescaler is cl eared. the i bit in the condi tion code register (ccr) is cleared to enable external interrupts. all other re gisters and memory remain unaltered. all input/output (i/o) lines remain unchanged. the processor can be brought out of stop mode only by an external interrupt or reset. see figure 6-1 . figure 6-1. stop recovery timing diagram $3ffe $3ffe $3ffe $3ffe $3fff internal address bus internal clock irq (3) irq (2) reset osc1 (1) t ilch 4064 t cyc reset or interrupt vector fetch t lih t rl notes: 1. represents the internal gating of the osc1 pin 2. irq pin edge-sensitive mask option 3. irq pin level and edge-sensitive mask option
low-power modes MC68HC05C9E advance information data sheet, rev. 0.1 36 freescale semiconductor 6.3 wait mode the wait instruction places the mcu in a low-powe r consumption mode, but wait mode consumes more power than stop mode. all central processor unit (cpu) action is suspended, but the timer, serial communications interface (sci), serial peripheral in terface (spi), and the oscillator remain active. any interrupt or reset will cause the mcu to exit wait mode. during wait mode, the i bit in the ccr is cleared to enable interrupts. all other registers, memory, and i/o lines remain in their previous state. the timer, sci, and spi may be enabled to allow a periodic exit from the wait mode.
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 37 chapter 7 input/output ports 7.1 introduction this section briefly describes the 31 input/output (i/o ) lines arranged as one 7-bit and three 8-bit ports. all of these port pins are programmable as either inputs or outputs under software control of the data direction registers. note to avoid a glitch on the output pins, write data to the i/o port data register before writing a 1 to the corresponding data direction register. 7.2 port a port a is an 8-bit bidirectional port which does not s hare any of its pins with other subsystems. the port a data register is at $0000 and the data direction regi ster (ddr) is at $0004. the contents of the port a data register are indeterminate at initial power-up and must be initialized by user software. reset does not affect the data registers, but clears the data direct ion registers, thereby returning the ports to inputs. writing a 1 to a ddr bit sets the corresponding port bi t to output mode. a block diagram of the port logic is shown in figure 7-1 . figure 7-1. port a i/o circuit data direction register bit latched output data bit i/o pin input reg. bit input i/o output internal hc05 connections
input/output ports MC68HC05C9E advance information data sheet, rev. 0.1 38 freescale semiconductor 7.3 port b port b is an 8-bit bidirectional port. the port b data register is at $0001 and the data direction register (ddr) is at $0005. the contents of the port b data register are indeterminate at initial powerup and must be initialized by user software. reset does not affect the data registers, but clears the data direction registers, thereby returning the por ts to inputs. writing a one to a ddr bit sets the corresponding port pin to output mode. each of the port b pins has an optional external interrupt capability that can be enabled by mask option. the interrupt option also enables a pullup device wh en the pin is configured as an input. the edge or edge- and level-sensitivity of the irq pin will also pertain to the enabled port b pins. care needs to be taken when using port b pins that have the pullup enabled. before switching from an output to an input, the data should be preconditioned to a 1 to prevent an interrupt from occurring. the port b logic is shown in figure 7-2 . 7.4 port c port c is an 8-bit bidirectional port. the port c data register is at $0002 and the data direction register (ddr) is at $0006. the contents of the port c data regi ster are indeterminate at initial powerup and must be initialized by user software. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writ ing a 1 to a ddr bit sets t he corresponding port bit to output mode. pc7 has a high current sink and source capability. figure 7-1 is also applicable to port c. 7.5 port d port d is a 7-bit bidirectional port. four of its pins are shared with the spi subsystem and two more are shared with the sci subsystem. the port d data regist er is at $0003 and the data direction register is at $0007. the contents of the port d data register are indeterminate at initial powerup and must be initialized by user software. during reset all seven bits become valid input ports because the ddr bits are cleared and the special function output drivers associated with the sci and spi subsyste ms are disabled, thereby returning the ports to inputs. writing a 1 to a ddr bit sets the corresponding port bit to output mode.
port d MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 39 figure 7-2. port b i/o logic data direction register b bit ddrb7 pbx external interrupt request port b data register bit pb7 read $0005 write $0001 read $0001 reset internal data bus write $0005 port b external interrupt from other v dd port b pins d c q r q i bit v dd from ccr reset external interrupt vector fetch irq mask option v dd enabled disabled edge only edge and level software controlled option
input/output ports MC68HC05C9E advance information data sheet, rev. 0.1 40 freescale semiconductor
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 41 chapter 8 capture/compare timer 8.1 introduction this section describes the operation of the 16-bit capture/compare timer. figure 8-1 shows the structure of the capture/compare subsystem. figure 8-1. capture/compare timer block diagram input capture register clock internal bus output compare register high byte low byte $16 $17 4 internal processor 16-bit free running counter counter alternate register 8-bit buffer high byte low byte $1a $1b $18 $19 high byte low byte $14 $15 output compare circuit overflow detect circuit edge detect circuit timer status reg. icf ocf tof $13 icie iedg olvl output level reg. reset timer control reg. $12 output level (tcmp) interrupt circuit toie ocie edge input (tcap) d clk c q
capture/compare timer MC68HC05C9E advance information data sheet, rev. 0.1 42 freescale semiconductor 8.2 timer operation the core of the capture/compare timer is a 16-bit free-running counter. the c ounter provides the timing reference for the input capture and output compare functions. the input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delay s. software can read the value in the 16-bit free-running counter at any time without affecting the counter sequence. because of the 16-bit timer architecture, the input/out put (i/o) registers for the input capture and output compare functions are pairs of 8-bit registers. because the counter is 16 bits long and preceded by a fixed divide-by-4 prescaler, the counter rolls over every 262,144 internal clock cycles. timer resolution with a 4-mhz crystal is 2 s. 8.2.1 input capture the input capture function is a means to record t he time at which an external event occurs. when the input capture circuitry detects an active edge on the tcap pin, it latches the contents of the timer registers into the input capture registers. the polarity of the active edge is programmable. latching values into the input capture registers at successive edges of the same polarity measures the period of the input signal on the tcap pin. latching va lues into the input capture registers at successive edges of opposite polarity measures the pulse width of the signal. 8.2.2 output compare the output compare function is a means of generatin g an output signal when the 16-bit counter reaches a selected value. software writes the selected value into the output compare registers. on every fourth internal clock cycle the output compar e circuitry compares the value of t he counter to the value written in the output compare registers. when a match occurs, the timer transfers the programmable output level bit (olvl) from the timer cont rol register to the tcmp pin. the programmer can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of specific duration or a pul se train of specific frequency and duty cycle on the tcmp pin. 8.3 timer i/o registers these i/o registers control and monitor timer operation: timer control register (tcr) timer status register (tsr) timer registers (trh and trl) alternate timer registers (atrh and atrl) input capture registers (icrh and icrl) output compare registers (ocrh and ocrl)
timer i/o registers MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 43 8.3.1 timer control register the timer control register (tcr), shown in figure 8-2 , performs these functions: enables input capture interrupts enables output compare interrupts enables timer overflow interrupts controls the active edge polarity of the tcap signal controls the active level of the tcmp output icie ? input capture interrupt enable bit this read/write bit enables interrupts caused by an active signal on the tcap pin. reset clears the icie bit. 1 = input capture interrupts enabled 0 = input capture interrupts disabled ocie ? output compare interrupt enable bit this read/write bit enables interrupts caused by an active signal on the tcmp pin. reset clears the ocie bit. 1 = output compare interrupts enabled 0 = output compare interrupts disabled toie ? timer overflow interrupt enable bit this read/write bit enables interrupts caused by a timer overflow. reset clears the toie bit. 1 = timer overflow interrupts enabled 0 = timer overflow interrupts disabled iedg ? input edge bit the state of this read/write bit determines whet her a positive or negative transition on the tcap pin triggers a transfer of the contents of the timer regi ster to the input capture register. resets have no effect on the iedg bit. 1 = positive edge (low to high transition) triggers input capture. 0 = negative edge (high to low tr ansition) triggers input capture. olvl ? output level bit the state of this read/write bit determines whether a logic 1 or logic 0 appears on the tcmp pin when a successful output compare occurs. reset clears the olvl bit. 1 = tcmp goes high on output compare. 0 = tcmp goes low on output compare. address: $0012 bit 7654321bit 0 read: icie ocie toie 000 iedg olvl write: reset:000000u0 = unimplemented u = undetermined figure 8-2. timer control register (tcr)
capture/compare timer MC68HC05C9E advance information data sheet, rev. 0.1 44 freescale semiconductor 8.3.2 timer status register the timer status register (tsr), shown in figure 8-3 , contains flags to signal these conditions: an active signal on the tcap pin, transferring the contents of the timer registers to the input capture registers a match between the 16-bit counter and the output compare registers, transferring the olvl bit to the tcmp pin a timer roll over from $ffff to $0000 icf ? input capture flag the icf bit is set automatically when an edge of th e selected polarity occurs on the tcap pin. clear the icf bit by reading the timer status register wi th icf set and then reading the low byte ($0015) of the input capture registers. resets have no effect on icf. ocf ? output compare flag the ocf bit is set automatically when the value of the timer registers matches the contents of the output compare registers. clear the ocf bit by reading the timer status register with ocf set and then reading the low byte ($0017) of the output compare registers. resets have no effect on ocf. tof ? timer overflow flag the tof bit is set automatically when the 16-bit counter rolls over from $ffff to $0000. clear the tof bit by reading the timer status register with to f set, and then reading the low byte ($0019) of the timer registers. resets have no effect on tof. address: $0013 bit 7654321bit 0 read:icfocftof00000 write: reset:uuu00000 = unimplemented u = unaffected figure 8-3. timer status register (tsr)
timer i/o registers MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 45 8.3.3 timer registers the timer registers (trh and trl), shown in figure 8-4 , contain the current high and low bytes of the 16-bit counter. reading trh before reading trl causes trl to be latched until trl is read. reading trl after reading the timer status register clears the timer overflow flag (tof). writing to the timer registers has no effect. 8.3.4 alternate timer registers the alternate timer registers (atrh and atrl), shown in figure 8-5 , contain the current high and low bytes of the 16-bit counter. reading atrh before read ing atrl causes atrl to be latched until atrl is read. reading atrl has no effect on the timer over flow flag (tof). writing to the alternate timer registers has no effect. note to prevent interrupts from occurring between readings of atrh and atrl, set the interrupt flag in the condition code register before reading atrh, and clear the flag after reading atrl. address: $0018 ? trh bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write reset:11111111 address: $0019 ? trl bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111100 = unimplemented figure 8-4. timer registers (trh and trl) address: $001a ? atrh bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $001b ? atrl bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111100 = unimplemented figure 8-5. alternate timer registers (atrh and atrl)
capture/compare timer MC68HC05C9E advance information data sheet, rev. 0.1 46 freescale semiconductor 8.3.5 input capture registers when a selected edge occurs on the tcap pin, the current high and low bytes of the 16-bit counter are latched into the input capture registers. reading i crh before reading icrl inhibits further capture until icrl is read. reading icrl after reading the status register clears the input capture flag (icf). writing to the input capture registers has no effect. note to prevent interrupts from occurri ng between readings of icrh and icrl, set the interrupt flag in the condition code register before reading icrh, and clear the flag after reading icrl. 8.3.6 output co mpare registers when the value of the 16-bit counter matches the va lue in the output compare registers, the planned tcmp pin action takes place. writing to ocrh before writing to ocrl inhibits timer compares until ocrl is written. reading or writing to ocrl after the time r status register clears the output compare flag (ocf). address: $0014 ? icrh bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset address: $0015 ? icrl bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset = unimplemented figure 8-6. input capture registers (icrh and icrl) address: $0016 ? ocrh bit 7654321bit 0 write: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 read: reset: unaffected by reset address: $0017 ? ocrl bit 7654321bit 0 write: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read: reset: unaffected by reset figure 8-7. output compare registers (ocrh and ocrl)
timer during wait mode MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 47 to prevent ocf from being set between the time it is read and the time the output compare registers are updated, use this procedure: 1. disable interrupts by setting the i bit in the ccr. 2. write to ocrh. compares are now inhibited until ocrl is written. 3. clear bit ocf by reading ti mer status register (tsr). 4. enable the output compare function by writing to ocrl. 5. enable interrupts by clearing the i bit in the ccr. 8.4 timer during wait mode the central processor unit (cpu) clock halts during wa it mode, but the timer remains active. if interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. 8.5 timer during stop mode in stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. if stop is exited by reset, the counters are forced to $fffc. during stop, if at least one valid input capture edge occurs at the tcap pins, the input captur e detect circuit is armed. this does not set any timer flags or wake up the microcontroller unit (mcu). but if an interrupt is used to exit stop mode, there is an active input capture flag and data from the first valid edge that occurred during the stop mode. if reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
capture/compare timer MC68HC05C9E advance information data sheet, rev. 0.1 48 freescale semiconductor
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 49 chapter 9 serial communications interface (sci) 9.1 introduction this section describes the on-chip asynchronous seri al communications interface (sci). the sci allows full-duplex, asynchronous, rs232 or rs422 serial communication between the microcontroller unit (mcu) and remote devices, including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. 9.2 features features of the sci include: standard mark/space non-return-to-zero format full-duplex operation 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation capability with five interrupt flags: ? transmitter data register empty ? transmission complete ? transmission data register full ? receiver overrun ? idle receiver input receiver framing error detection 1/16 bit-time noise detection note the serial communications data register (sci scdr) is controlled by the internal r/w signal. it is the transmit data register when written to and the receive data register when read.
serial communications interface (sci) MC68HC05C9E advance information data sheet, rev. 0.1 50 freescale semiconductor figure 9-1. serial communications interface block diagram 9.3 sci receiver features features of the sci receiver include: receiver wakeup function (idle line or address bit) idle line detection framing error detection noise detection overrun detection receiver data register full flag + + internal bus sci interrupt transmit receive tdo pin rdi transmitter control receiver control clock pin receiver flag control data data tie tcie rie ilie te re sbk rwu 7 6 5 4 3 2 1 0 $000f sccr2 scsr $0010 sccr1 $000e trde tc rdrf idle or nf fe te sbk $0011 r8 t8 m wake 0 1 2 4 3 6 5 7 765 2 3 4 1 wakeup unit receive data shift register transmit data shift register $0011 7 &&&& register register
sci transmitter features MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 51 9.4 sci transmitter features features of the sci transmitter include: transmit data register empty flag transmit complete flag send break 9.5 functional description a block diagram of the sci is shown in figure 9-1 . option bits in serial control register1 (sccr1) select the wakeup method (wake bit) and data word length (m bit) of the sci. sccr2 provides control bits that individually enable the transmitter and receiver, enabl e system interrupts, and provide the wakeup enable bit (rwu) and the send break code bit (sbk). control bits in the baud rate register (baud) allow the user to select one of 32 different baud rates for the transmitter and receiver. data transmission is initiated by writing to the se rial communications data regi ster (scdr). provided the transmitter is enabled, data stored in the scdr is tr ansferred to the transmit data shift register. this transfer of data sets the transmit data register empty flag (tdre) in the sci status register (scsr) and generates an interrupt (if transmitter interrupts are enabl ed). the transfer of data to the transmit data shift register is synchronized with the bit rate clock (see figure 9-2 ). all data is transmitt ed least significant bit first. upon completion of data transmission, the tr ansmission complete flag (t c) in the scsr is set (provided no pending data, preamble, or break is to be sent) and an interrupt is generated (if the transmit complete interrupt is enabled). if the transmitter is disabled, and the data, preamble, or break (in the transmit data shift register) has been sent, the tc bit will be set also. this will also generate an interrupt if the transmission complete interrupt enable bit (tcie) is set. if the transmitter is disabled during a transmission, the character being transmitted will be completed before the transmitter gives up control of the tdo pin. when scdr is read, it contains the last data byte received, provided that the receiver is enabled. the receive data register full flag bit (rdrf) in the sc sr is set to indicate that a data byte has been transferred from the input serial shift register to the scdr; this will cause an interrupt if the receiver interrupt is enabled. the data transfer from the input se rial shift register to the scdr is synchronized by the receiver bit rate clock. the or (overrun), nf (noi se), or fe (framing) error flags in the scsr may be set if data reception errors occurred. an idle line interrupt is generated if the idle line inte rrupt is enabled and the idle bit (which detects idle line transmission) in scsr is set. th is allows a receiver that is not in the wakeup mode to detect the end of a message, or the preamble of a new message, or to re-synchronize with the transmitter. a valid character must be received before the idle line cond ition or the idle bit will not be set and idle line interrupt will not be generated. figure 9-2. rate generator division osc freq (f osc ) 2 bus freq (f op ) scp0?scp1 sci prescaler select n scr0?scr2 sci rate select m 16 sci trans clock (tx) sci receive clock (rt) control control
serial communications interface (sci) MC68HC05C9E advance information data sheet, rev. 0.1 52 freescale semiconductor 9.6 data format receive data or transmit data is the serial data that is transferred to the internal data bus from the receive data input pin (rdi) or from the internal bus to t he transmit data output pin (tdo). the non-return-to-zero (nrz) data format shown in figure 9-3 is used and must meet these criteria: the idle line is brought to a logic 1 state prior to transmission/ reception of a character. a start bit (logic 0) is used to indicate the start of a frame. the data is transmitted and received least significant bit first. a stop bit (logic 1) is used to indicate the end of a frame. a frame consists of a start bit, a character of eight or nine data bits, and a stop bit. a break is defined as the transmission or reception of a low (logic 0) for at least one complete frame time. figure 9-3. data format 9.7 receiver wakeup operation the receiver logic hardware also supports a receiver wakeup function which is intended for systems having more than one receiver. with this function a transmitting device directs messages to an individual receiver or group of receivers by passing addressing information as the initial byte(s) of each message. the wakeup function allows receivers not addressed to remain in a dormant state for the remainder of the unwanted message. this eliminates any further software overhead to service the remaining characters of the unwanted message and thus im proves system performance. the receiver is placed in wakeup mode by setting t he receiver wakeup bit (rwu) in the sccr2 register. while rwu is set, all of the receiver-related stat us flags (rdrf, idle, or, nf, and fe) are inhibited (cannot become set). note the idle line detect function is inhibited while the rwu bit is set. although rwu may be cleared by a software write to sccr2, it would be unusual to do so. normally, rwu is set by software and is cleared automatically in hardware by one of these methods: idle line wakeup or address mark wakeup. 9.7.1 idle line wakeup in idle line wakeup mode, a dormant receiver wakes up as soon as the rdi line becomes idle. idle is defined as a continuous logic high level on the rdi li ne for 10 (or 11) full bit times. systems using this type of wakeup must provide at least one character time of idle between messages to wake up sleeping receivers, but must not allow any idle time between characte rs within a message. idle line 012345678 0 stop start start control bit m selects 8- or 9-bit data
receive data in (rdi) MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 53 9.7.2 address mark wakeup in address mark wakeup, the most significant bit (msb) in a character is used to indicate whether it is an address (logic 1) or data (logic 0) character. sleeping receivers will wake up whenever an address character is received. systems using this method for wakeup would set the msb of the first character of each message and leave it clear for all other characte rs in the message. idle periods may be present within messages and no idle time is required between messages for this wakeup method. 9.8 receive data in (rdi) receive data is the serial data that is applied through the input line and the sci to the internal bus. the receiver circuitry clocks the input at a rate equal to 16 times the baud rate. this time is referred to as the rt rate in figure 9-4 and as the receiver clock in figure 9-6 . figure 9-4. sci examples of start bit sampling techniques the receiver clock generator is controlled by the baud rate register; however, the sci is synchronized by the start bit, independent of the transmitter. once a valid start bit is detected, the start bit, each data bit, and the stop bit are sampled three times at rt intervals 8rt, 9rt, and 10rt (1rt is the position where the bit is expected to start), as shown in figure 9-5 . the value of the bit is determined by voting logic which takes the value of the majority of the samples. a noise flag is set when all three samples on a valid start bit or data bit or the stop bit do not agree. figure 9-5. sci sampling technique used on all bits 111111110000 111111110010 111011110 0 0 0 noise noise start start start rdi rdi rdi idle 1rt 2rt 3rt 4rt 5rt 6rt 7rt rt clock edges for all three examples 16x internal sampling clock 9rt 8rt 10rt 16rt 1rt 16rt 1rt samples next bit previous bit rdi
serial communications interface (sci) MC68HC05C9E advance information data sheet, rev. 0.1 54 freescale semiconductor 9.9 start bit detection when the input (idle) line is detected low, it is tested for three more sample times (referred to as the start edge verification samples in figure 9-4 ). if at least two of these three verification samples detect a logic 0, a valid start bit has been detected; otherwise, the line is assumed to be idle. a noise flag is set if all three verification samples do not detect a logic 0. thus, a va lid start bit could be assumed with a set noise flag present. if a framing error has occurred without detection of a break (10 0s for 8-bit format or 11 0s for 9-bit format), the circuit continues to operate as if there actually was a stop bit, and the start edge will be placed artificially. the last bit received in the data shift register is inverted to a logic 1, and the three logic 1 start qualifiers (shown in figure 9-4 ) are forced into the sample shift register during the interval when detection of a start bit is anticipated (see figure 9-6 ); therefore, the start bit will be accepted no sooner than it is anticipated. figure 9-6. sci artificial start following a frame error if the receiver detects that a break (rdrf = 1, fe = 1, receiver data register = $003b) produced the framing error, the start bit will not be artificially induced and the rece iver must actually detect a logic 1 before the start bit can be recognized (see figure 9-7 ). figure 9-7. sci start bit following a break data expected stop data samples artificial edge start bit data rdi data expected stop data samples start edge start bit data rdi a) case 1: receive line low during artificial edge b) case 2: receive line high during expect ed start edge expected stop data samples detected as valid start edge start bit rdi break start qualifiers start edge verification samples
transmit data out (tdo) MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 55 9.10 transmit data out (tdo) transmit data is the serial data from the internal data bus that is applied through the sci to the output line. data format is as discussed in 9.6 data format and shown in figure 9-3 . the transmitter generates a bit time by using a derivative of the rt clock, thus producing a transmission rate equal to 1/16th that of the receiver sample clock. 9.11 sci i/o registers these i/o registers control and monitor sci operation: sci data register (scdr) sci control register 1 (sccr1) sci control register 2 (sccr2) sci status register (scsr) 9.11.1 sci data register the sci data register (scdr), shown in figure 9-8 , is the buffer for characters received and for characters transmitted. 9.11.2 sci cont rol register 1 the sci control register 1 (sccr1), shown in figure 9-9 , has these functions: stores ninth sci data bit received and ninth sci data bit transmitted controls sci character length controls sci wakeup method r8 ? bit 8 (received) when the sci is receiving 9-bit characters, r8 is the ninth bit of the received character. r8 receives the ninth bit at the same time that the scdr receives the other eight bi ts. resets have no effect on the r8 bit. t8 ? bit 8 (transmitted) when the sci is transmitting 9-bit characters, t8 is the ninth bit of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit register. resets have no effect on the t8 bit. address: $0011 bit 7654321bit 0 read: scd7 sdc6 scd5 scd4 scd3 scd2 scd1 scd0 write: reset: unaffected by reset figure 9-8. sci data register (scdr) address: $000e bit 7654321bit 0 read: r8 t8 m wake write: reset: u u 0 u u 0 0 0 = unimplemented u = undetermined figure 9-9. sci control register 1 (sccr1)
serial communications interface (sci) MC68HC05C9E advance information data sheet, rev. 0.1 56 freescale semiconductor m ? character length bit this read/write bit determines whether sci characters are 8 bits long or 9 bits long. the ninth bit can be used as an extra stop bit, as a receiver wakeup si gnal, or as a mark or space parity bit. resets have no effect on the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup method bit this read/write bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit (msb) position of a received characte r or an idle condition on the pd0/rdi pin. resets have no effect on the wake bit. 1 = address mark wakeup 0 = idle line wakeup 9.11.3 sci cont rol register 2 sci control register 2 (sccr2), shown in figure 9-10 , has these functions: enables the sci receiver and sci receiver interrupts enables the sci transmitter and sci transmitter interrupts enables sci receiver idle interrupts enables sci transmission complete interrupts enables sci wakeup transmits sci break characters tie ? transmit interrupt enable bit this read/write bit enables sci interrupt requests when the tdre flag becomes set. resets clear the tie bit. 1 = tdre interrupt requests enabled 0 = tdre interrupt requests disabled tcie ? transmission complete interrupt enable bit this read/write bit enables sci interrupt requests when the tc flag becomes set. resets clear the tcie bit. 1 = tc interrupt requests enabled 0 = tc interrupt requests disabled rie ? receiver interrupt enable bit this read/write bit enables sci in terrupt requests when the rdrf fl ag or the or flag becomes set. resets clear the rie bit. 1 = rdrf interrupt requests enabled 0 = rdrf interrupt requests disabled address: $000f bit 7654321bit 0 read: tie tcie rie ilie te re rwu sbk write: reset:00000000 figure 9-10. sci control register 2 (sccr2)
sci i/o registers MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 57 ilie ? idle line interrupt enable bit this read/write bit enables sci interrupt requests when the idle bit becomes set. resets clear the ilie bit. 1 = idle interrupt requests enabled 0 = idle interrupt requests disabled te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the pd1/tdo pin. resets clear the te bit. 1 = transmission enabled 0 = transmission disabled re ? receiver enable bit setting this read/write bit enables the receiver. clear ing the re bit disables the receiver and receiver interrupts but does not affect the receiver interrupt flags. resets clear the re bit. 1 = receiver enabled 0 = receiver disabled rwu ? receiver wakeup enable bit this read/write bit puts the receiver in a standby state. typically, data transmitted to the receiver clears the rwu bit and returns the receiver to norma l operation. the wake bit in sccr1 determines whether an idle input or an address mark brings the receiver out of standby state. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting this read/write bit continuously transmits break codes in the form of 10-bit or 11-bit groups of logic 0s. clearing the sbk bit stops the break codes and transmits a l ogic 1 as a start bit. reset clears the sbk bit. 1 = break codes being transmitted 0 = no break codes being transmitted 9.11.4 sci status register the sci status register (scsr), shown in figure 9-11 , contains flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data scdr complete receiver input idle noisy data framing error address: $0010 bit 7654321bit 0 read: tdre tc rdrf idle or nf fe write: reset:1100000? = unimplemented figure 9-11. sci status register (scsr)
serial communications interface (sci) MC68HC05C9E advance information data sheet, rev. 0.1 58 freescale semiconductor tdre ? transmit data register empty flag this clearable, read-only flag is set when the data in the scdr transfers to the transmit shift register. tdre generates an interrupt request if the tie bit in sccr2 is also set. clear the tdre bit by reading the scsr with tdre set and then writing to th e scdr. reset sets the tdre bit. software must initialize the tdre bit to logic 0 to avoid an instant interrupt request when turning the transmitter on. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ? transmission complete flag this clearable, read-only flag is set when the tdre bit is set, and no data, preamble, or break character is being transmitt ed. tdre generates an interrupt request if the tcie bit in sccr2 is also set. clear the tc bit by reading the scsr with tc set, and then writing to t he scdr. reset sets the tc bit. software must initialize the tc bit to logi c 0 to avoid an instant interrupt request when turning the transmitter on. 1 = no transmission in progress 0 = transmission in progress rdrf ? receive data register full flag this clearable, read-only flag is set when the data in the receive shift register transfers to the sci data register. rdrf generates an interrupt request if the ri e bit in the sccr2 is al so set. clear the rdrf bit by reading the scsr with r drf set and then reading the scdr. 1 = received data available in scdr 0 = received data not available in scdr idle ? receiver idle flag this clearable, read-only flag is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an interrupt request if the ilie bit in the sccr2 is also set. clear the ilie bit by reading the scsr with idle set and then reading the scdr. 1 = receiver input idle 0 = receiver input not idle or ? receiver overrun flag this clearable, read-only flag is set if the scdr is not read before the receive shift register receives the next word. or generates an interrupt request if th e rie bit in the sccr2 is also set. the data in the shift register is lost, but the data already in t he scdr is not affected. clear the or bit by reading the scsr with or set and then reading the scdr. 1 = receive shift register full and rdrf = 1 0 = no receiver overrun nf ? receiver noise flag this clearable, read-only flag is set when noise is detected in data received in the sci data register. clear the nf bit by reading the scsr and then reading the scdr. 1 = noise detected in scdr 0 = no noise detected in scdr fe ? receiver framing error flag this clearable, read-only flag is set when there is a logic 0 where a stop bit should be in the character shifted into the receive shift register. if the rece ived word causes both a framing error and an overrun error, the or flag is set and the fe flag is not set. clear the fe bit by reading the scsr and then reading the scdr. 1 = framing error 0 = no framing error
sci i/o registers MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 59 9.11.5 baud rate register the baud rate register (baud), shown in figure 9-12 , selects the baud rate for both the receiver and the transmitter. scp1 ? scp0?sci prescaler select bits these read/write bits control prescaling of the baud rate generator clock, as shown in table 9-1 . reset clears both scp1 and scp0. scr2 ? scr0?sci baud rate select bits these read/write bits select the sci baud rate, as shown in table 9-2 . resets have no effect on the scr2?scr0 bits. address: $000d bit 7654321bit 0 read: scp1 scp0 scr2 scr1 scr0 write: reset: ? ? 0 0 ? u u u = unimplemented u = unaffected figure 9-12. baud rate register (baud) table 9-1. baud rate generator clock prescaling scp1 and scp0 baud ra te generator clock 0 0 internal clock 1 0 1 internal clock 3 1 0 internal clock 4 1 1 internal clock 13 table 9-2. baud rate selection scr2, scr1, and scr0 sci baud rate (baud) 0 0 0 prescaled clock 1 0 0 1 prescaled clock 2 0 1 0 prescaled clock 4 0 1 1 prescaled clock 8 1 0 0 prescaled clock 16 1 0 1 prescaled clock 32 1 1 0 prescaled clock 64 1 1 1 prescaled clock 128
serial communications interface (sci) MC68HC05C9E advance information data sheet, rev. 0.1 60 freescale semiconductor
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 61 chapter 10 serial peripheral interface (spi) 10.1 introduction the serial peripheral interface (spi) is an interfac e built into the device which allows several m68hc05 microcontroller units (mcu), or m68hc05 mcu plus peripheral devices, to be interconnected within a single printed circuit board. in an spi, separate wires are required for data and clock. in the spi format, the clock is not included in the data stream and must be furnished as a separat e signal. an spi system may be configured in one containing one master mcu and several slave mcus or in a system in which an mcu is capable of being a master or a slave. 10.2 features spi features include: full-duplex, 4-wire synchronous transfers master or slave operation bus frequency divided by 2 (maximum) master bit frequency bus frequency (maximum) slave bit frequency four programmable master bit rates programmable clock polarity and phase end-of-transmission interrupt flag write collision flag protection master-master mode fault protection capability 10.3 spi signal description the four basic signals (mosi, miso, sck, and ss ) are described here. each signal function is described for both the master and slave modes. note any spi output line has to have its corresponding data direction register bit set. if this bit is clear, the line is disconnected from the spi logic and becomes a general-purpose input line. when the spi is enabled, any spi input line is forced to act as an input regardless of what is in the corresponding data direction register bit. 10.3.1 master in/slave out (miso) the miso line is configured as an input in a master device and as an output in a slave device. it is one of the two lines that transfer serial data in one direction, with the most si gnificant bit sent first. the miso line of a slave device is placed in the high- impedance state if the slave is not selected.
serial peripheral interface (spi) MC68HC05C9E advance information data sheet, rev. 0.1 62 freescale semiconductor figure 10-1. data clock timing diagram 10.3.2 master ou t/slave in (mosi) the mosi line is configured as an output in a master device and as an input in a slave device. it is one of the two lines that transfer serial data in one di rection with the most significant bit sent first. 10.3.3 serial clock (sck) the master clock is used to synchronize data moveme nt both in and out of the device through its mosi and miso lines. the master and slave devices are capa ble of exchanging a byte of information during a sequence of eight clock cycles. sinc e sck is generated by the master device, this line becomes an input on a slave device. as shown in figure 10-1 , four possible timing relationships may be chosen by using control bits cpol and cpha in the serial peripheral control register (spcr). both master and slave devices must operate with the same timing. the master device always places dat a on the mosi line a half cycle before the clock edge (sck), in order for the slave device to latch the data. two bits (spr0 and spr1) in the spcr of the master device select the clock rate. in a slave device, spr0 and spr1 have no effect on the operation of the spi. 10.3.4 slave select (ss ) the slave select (ss ) input line is used to select a slave device. it has to be low prior to data transactions and must stay low for the duration of the transaction.the ss line on the master must be tied high. in master mode, if the ss pin is pulled low during a transmission, a mode fault error flag (modf) is set in the spsr. in master mode the ss pin can be selected as a general-pur pose output by writing a 1 in bit 5 of the port d data direction register, thus disabling the mode fault circuit. msb 5 3 64 21 0 internal strobe for data capture (all modes) miso/mosi sck sck sck sck ss cpol = 0 cpha = 0 cpol = 0 cpha = 1 cpol = 1 cpha = 1 cpol = 1 cpha = 0
functional description MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 63 when cpha = 0, the shift clock is the or of ss with sck. in this clock phase mode, ss must go high between successive characters in an spi message. when cpha = 1, ss may be left low for several spi characters. in cases where there is only one spi slave mcu, its ss line could be tied to v ss as long as cpha = 1 clock modes are used. 10.4 functional description figure 10-2 shows a block diagram of the serial peripher al interface circuitry. when a master device transmits data to a slave via the mosi line, the sl ave device responds by sending data to the master device via the master?s miso line. this implies fu ll duplex transmission with both data out and data in synchronized with the same clock signal. thus, the by te transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiv e-full status bits. a single status bit (spif) is used to signify that the input/output (i/o) operation has been completed. figure 10-2. serial peripheral interface block diagram the spi is double buffered on read, but not on write. if a write is performed during data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. this condition will cause the write collision (wcol) status bit in the spsr to be set. a fter a data byte is shifted, the spif flag of the spsr is set. s 6 7 543210 spe spie spi control register (spcr) mstr cpol cpha spr1 spr2 $000a wcol spif spi status register (spsr) 0 modf 0 0 $000b bit 6 bit 7 spi data register (spdr) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $000c dwom 00 spi shift register divider clock logic spdr ($000c) 7 6 5 4 3 2 1 0 modf wcol spif spr1 spr0 cpol cpha mstr spe spie pd3/ mosi pd2/ miso 2 32 16 4 select spi control internal data bus mstr s m m internal clock (xtal 2) spi clock (master) spi interrupt request shift clock pd4/ sck pd5/ ss slave spi spi master clock clock
serial peripheral interface (spi) MC68HC05C9E advance information data sheet, rev. 0.1 64 freescale semiconductor in the master mode, the sck pin is an output. it idles high or low, depending on the cpol bit in the spcr, until data is written to the shift register, at which poin t eight clocks are generated to shift the eight bits of data and then sck goes idle again. in a slave mode, the slave select start logic receives a logic low at the ss pin and a clock at the sck pin. thus, the slave is synchronized with the master. data from the master is received serially at the mosi line and loads the 8-bit shift register. after the 8-bit shi ft register is loaded, its data is parallel transferred to the read buffer. during a write cycle, data is written into the shift register, then the slave waits for a clock train from the master to shift the data out on the slave?s miso line. figure 10-3 illustrates the mosi, miso, sck, and ss master-slave interconnections. figure 10-3. serial peripheral interface master-slave interconnection 10.5 spi registers this subsection describes the three registers in the spi which provide control, status, and data storage functions. these registers are: serial peripheral control register (spcr) serial peripheral status register (spsr) serial peripheral data i/o register (spdr) 10.5.1 serial peripher al control register the spi control register (spcr), shown in figure 10-4 , controls these functions: enables spi interrupts enables the spi system selects between standard cmos or open drain outputs for port d selects between master mode and slave mode controls the clock/data relationship between master and slave determines the idle level of the clock pin address: $000a bit 7654321bit 0 read: spie spe dwom mstr cpol cpha spr1 spr0 write: reset:000001uu u = undetermined figure 10-4. spi control register (spcr) spi shift register 7 6 5 4 3 2 1 0 spi shift register 7 6 5 4 3 2 1 0 spdr ($000c) spdr ($000c) pd3/mosi pd2/miso pd5/ss pd4/sck master mcu slave mcu i/o port
spi registers MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 65 spie ? serial peripheral interrupt enable bit this read/write bit enables spi interrupts. reset clears the spie bit. 1 = spi interrupts enabled 0 = spi interrupts disabled spe ? serial peripheral system enable bit this read/write bit enables the spi. reset clears the spe bit. 1 = spi system enabled 0 = spi system disabled dwom ? port d wire-or mode option bit this read/write bit disables the high side driver transistors on port d outputs so that port d outputs become open-drain drivers. dwom affects all seven port d pins together. 1 = port d outputs act as open-drain outputs. 0 = port d outputs are normal cmos outputs. mstr ? master mode select bit this read/write bit selects master mode operation or slave mode operation. reset clears the mstr bit. 1 = master mode 0 = slave mode cpol ? clock polarity bit when the clock polarity bit is cleared and data is not being transferred, a steady state low value is produced at the sck pin of the master device. conversely, if this bit is set, the sck pin will idle high. this bit is also used in conjunction with the cloc k phase control bit to produce the desired clock-data relationship between master and slave. see figure 10-1 . cpha ? clock phase bit the clock phase bit, in conjunction wi th the cpol bit, controls the clock-data relationship between master and slave. the cpol bit can be thought of as si mply inserting an inverter in series with the sck line. the cpha bit selects one of two fu ndamentally different clocking protocols. when cpha = 0, the shift clock is the or of sck with ss . as soon as ss goes low, the transaction begins and the first edge on sck invokes the first data sample. when cpha=1, the ss pin may be thought of as a simple output enable control. see figure 10-1 . spr1 and spr0 ? spi clock rate select bits these read/write bits select one of four master mode serial clock rates, as shown in table 10-1 . they have no effect in slave mode. table 10-1. spi clock rate selection spr1 and spr0 spi clock rate 0 0 internal clock 2 0 1 internal clock 4 1 0 internal clock 16 1 1 internal clock 32
serial peripheral interface (spi) MC68HC05C9E advance information data sheet, rev. 0.1 66 freescale semiconductor 10.5.2 serial peripher al status register the spi status register (spsr), shown in figure 10-5 , contains flags to signal these conditions: spi transmission complete write collision mode fault spif ? spi transfer complete flag the serial peripheral data transfer flag bit is set upon completion of data transfer between the processor and external device. if spif goes high, and if spie is set, a serial peripheral interrupt is generated. clearing the spif bit is accomplished by reading the spsr (with spif set) followed by an access of the spdr. following the initial transfer, unless spsr is read (with spif set) first, attempts to write to spdr are inhibited. wcol ? write collision bit the write collision bit is set when an attempt is made to write to the serial peripheral data register while data transfer is taking place. if cpha is 0, a transfer is said to begin when ss goes low and the transfer ends when ss goes high after eight clock cycles on sck. when cpha is 1, a transfer is said to begin the first time sck becomes active while ss is low and the transfer ends when the spif flag gets set. clearing the wcol bit is accomplished by reading t he spsr (with wcol set) followed by an access to spdr. modf ? mode fault flag the mode fault flag indicates that there may have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state. the modf bit is normally clear, and is set only when the master device has its ss pin pulled low. setting the modf bit affects the internal serial peripheral interface system in these ways: 1. an spi interrupt is generated if spie = 1. 2. the spe bit is cleared. this disables the spi. 3. the mstr bit is cleared, thus fo rcing the device into the slave mode. clearing the modf bit is accomplished by reading th e spsr (with modf set), followed by a write to the spcr. control bits spe and mstr may be restored by user software to t heir original state during this clearing sequence or after the modf bit has been cleared. it is also necessary to restore ddrd after a mode fault. bits 5 and 3?0 ? not implemented these bits always read 0. address: $000b bit 7654321bit 0 read:spifwcol0modf0000 write: reset:00000000 = unimplemented figure 10-5. spi status register
spi registers MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 67 10.5.3 serial peripheral data i/o register the serial peripheral data i/o register (spdr), shown in figure 10-6 , is used to transmit and receive data on the serial bus. only a write to this register will in itiate transmission/reception of another byte and this will only occur in the master device. at the completion of transmitting a byte of data, the spif status bit is set in both the master and slave devices. when the user reads the serial peripheral data i/o r egister, a buffer is actually being read. the first spif must be cleared by the time a second transfer of the data from the shift register to the read buffer is initiated or an overrun condition will exist. in cases of overrun, the byte which causes the overrun is lost. a write to the serial peripheral data i/o register is not buffered and places data directly into the shift register for transmission. address: $000c bit 7654321bit 0 read: spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 write: reset: unaffected by reset figure 10-6. spi data register (spdr)
serial peripheral interface (spi) MC68HC05C9E advance information data sheet, rev. 0.1 68 freescale semiconductor
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 69 chapter 11 instruction set the microcontroller unit (mcu) instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos (complementary metal-oxide semiconductor) family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. 11.1 addressing modes the central processor unit (cpu) uses eight addressi ng modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative 11.1.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in th e cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 11.1.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instruct ions require no operand addres s and are two bytes long. the opcode is the first byte, and the i mmediate data value is the second byte. 11.1.3 direct direct instructions can access any of the first 256 me mory locations with two byte s. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address.
instruction set MC68HC05C9E advance information data sheet, rev. 0.1 70 freescale semiconductor 11.1.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 11.1.5 indexed, no offset indexed instructions with no offset are 1-byte inst ructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as t he high byte, so these instructions can address locations $0000?$00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used random-access memory (ram) or input/output (i/o) location. 11.1.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instru ctions that can access data with variable addresses within the first 511 memo ry locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the e ffective address of the operand. these instructions can access locations $0000?$01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory lo cations and could extend as far as location 510 ($01fe). the k value is typically in the index regist er, and the address of the beginning of the table is in the byte following the opcode. 11.1.7 indexed, 16-bit offset indexed, 16-bit offset instructions are 3-byte instruct ions that can access data with variable addresses at any location in memory. the cpu adds the unsigned by te in the index register to the two unsigned bytes following the opcode. the sum is the effective addres s of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for se lecting the kth element in an n-element table anywhere in memory. as with direct and extended address ing, the freescale assembler determines the shortest form of indexed addressing. 11.1.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two?s complement byte that gives a branching range of ?128 to +127 bytes from the address of the next location after the branch instruction. when using the freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.
instruction types MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 71 11.2 instruction types the mcu instructions fall in to these five categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions 11.2.1 register/memory instructions these instructions operate on central processor unit (cpu) registers and memory locations. most of them use two operands. one operand is in either the accumula tor or the index register. the cpu finds the other operand in memory. table 11-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub
instruction set MC68HC05C9E advance information data sheet, rev. 0.1 72 freescale semiconductor 11.2.2 read-modify-w rite instructions these instructions read a memory location or a regist er, modify its contents, and write the modified value back to the memory location or to the register. note do not use read-modify-write operations on write-only registers. table 11-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) 1. unlike other read-modify-wri te instructions, bclr and bset use only direct addressing. bit set bset (1) clear register clr complement (one?s complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (two?s complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) 2. tst is an exception to the read-modify-write sequence because it does not write a replacement value.
instruction types MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 73 11.2.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch bas ed on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be test ed is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ?128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the test ed bit to the carry/borrow bit of the condition code register. table 11-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr
instruction set MC68HC05C9E advance information data sheet, rev. 0.1 74 freescale semiconductor 11.2.4 bit manipul ation instructions the cpu can set or clear any writable bit in the fi rst 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. 11.2.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 11-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset table 11-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait
instruction set summary MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 75 11.3 instruction set summary table 11-6. instruction se t summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a (a) (m) ? ? ? imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) ? ? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right ? ? dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bclr n opr clear bit n mn 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? z = 1 ????? rel 27 rr 3 bhcc rel branch if half-carry bit clear pc (pc) + 2 + rel ? h = 0 ????? rel 28 rr 3 bhcs rel branch if half-carry bit set pc (pc) + 2 + rel ? h = 1 ????? rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? c z = 0 ????? rel 22 rr 3 bhs rel branch if higher or same pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ????? rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ????? rel 2e rr 3 c b0 b7 0 b0 b7 c
instruction set MC68HC05C9E advance information data sheet, rev. 0.1 76 freescale semiconductor bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) ? ? ? imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? c z = 1 ????? rel 23 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? i = 0 ????? rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? n = 1 ????? rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? i = 1 ????? rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? z = 0 ????? rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? n = 0 ????? rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ? 1 = 1 ????? rel 20 rr 3 brclr n opr rel branch if bit n clear pc (pc) + 2 + rel ? mn = 0 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 + rel ? 1 = 0 ????? rel 21 rr 3 brset n opr rel branch if bit n set pc (pc) + 2 + rel ? mn = 1 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ????? rel ad rr 6 clc clear carry bit c 0 ???? 0 inh 98 2 cli clear interrupt mask i 0 ? 0 ??? inh 9a 2 table 11-6. instruction se t summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc
instruction set summary MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 77 clr opr clra clrx clr opr ,x clr ,x clear byte m $00 a $00 x $00 m $00 m $00 ?? 0 1 ? dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ? (m) ? ? imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (a) x (x ) = $ff ? (x) m (m ) = $ff ? (m) m (m ) = $ff ? (m) ?? 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ? (m) ? ? imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a (a) (m) ? ? ? imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc jump address ????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n (n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc effective address ????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 table 11-6. instruction se t summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc
instruction set MC68HC05C9E advance information data sheet, rev. 0.1 78 freescale semiconductor lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a (m) ? ? ? imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x (m) ? ? ? imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) ? ? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right ? ? 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a (x) (a) 0 ??? 0 inh 42 1 1 neg opr nega negx neg opr ,x neg ,x negate byte (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation ????? inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a (a) (m) ? ? ? imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit ? ? dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit ? ? dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp $00ff ? ???? inh 9c 2 table 11-6. instruction se t summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7 b0 b7 c
instruction set summary MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 79 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ????? inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a (a) ? (m) ? (c) ? ? imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c 1 ???? 1 inh 99 2 sei set interrupt mask i 1 ? 1 ??? inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m (a) ? ? ? dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin ? 0 ? ? ? inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m (x) ? ? ? dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a (a) ? (m) ? ? imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ? 1 ??? inh 83 1 0 tax transfer accumulator to index register x (a) ????? inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ? $00 ? ? ? dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 table 11-6. instruction se t summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc
instruction set MC68HC05C9E advance information data sheet, rev. 0.1 80 freescale semiconductor 11.4 opcode map see table 11-7 . txa transfer index register to accumulator a (x) ????? inh 9f 2 wait stop cpu clock and enable interrupts ? 0 ? ? ? inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch p rogram counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit o ffset addressing rr relative pr ogram counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix1 indexed, 8-bit offset addressing mode loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit ? not affected table 11-6. instruction se t summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 81 opcode map table 11-7. opcode map bit manipulation branch read-modif y-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3dir 5 bset0 2dir 3 bra 2rel 5 neg 2dir 3 nega 1inh 3 negx 1inh 6 neg 2ix1 5 neg 1ix 9 rti 1inh 2 sub 2imm 3 sub 2dir 4 sub 3 ext 5 sub 3ix2 4 sub 2ix1 3 sub 1ix 0 1 5 brclr0 3dir 5 bclr0 2dir 3 brn 2rel 6 rts 1inh 2 cmp 2imm 3 cmp 2dir 4 cmp 3 ext 5 cmp 3ix2 4 cmp 2ix1 3 cmp 1ix 1 2 5 brset1 3dir 5 bset1 2dir 3 bhi 2rel 11 mul 1inh 2 sbc 2imm 3 sbc 2dir 4 sbc 3 ext 5 sbc 3ix2 4 sbc 2ix1 3 sbc 1ix 2 3 5 brclr1 3dir 5 bclr1 2dir 3 bls 2rel 5 com 2dir 3 coma 1inh 3 comx 1inh 6 com 2ix1 5 com 1ix 10 swi 1inh 2 cpx 2imm 3 cpx 2dir 4 cpx 3 ext 5 cpx 3ix2 4 cpx 2ix1 3 cpx 1ix 3 4 5 brset2 3dir 5 bset2 2dir 3 bcc 2rel 5 lsr 2dir 3 lsra 1inh 3 lsrx 1inh 6 lsr 2ix1 5 lsr 1ix 2 and 2imm 3 and 2dir 4 and 3 ext 5 and 3ix2 4 and 2ix1 3 and 1ix 4 5 5 brclr2 3dir 5 bclr2 2dir 3 bcs/blo 2rel 2 bit 2imm 3 bit 2dir 4 bit 3 ext 5 bit 3ix2 4 bit 2ix1 3 bit 1ix 5 6 5 brset3 3dir 5 bset3 2dir 3 bne 2rel 5 ror 2dir 3 rora 1inh 3 rorx 1inh 6 ror 2ix1 5 ror 1ix 2 lda 2imm 3 lda 2dir 4 lda 3 ext 5 lda 3ix2 4 lda 2ix1 3 lda 1ix 6 7 5 brclr3 3dir 5 bclr3 2dir 3 beq 2rel 5 asr 2dir 3 asra 1inh 3 asrx 1inh 6 asr 2ix1 5 asr 1ix 2 ta x 1inh 4 sta 2dir 5 sta 3 ext 6 sta 3ix2 5 sta 2ix1 4 sta 1ix 7 8 5 brset4 3dir 5 bset4 2dir 3 bhcc 2rel 5 asl/lsl 2dir 3 asla/lsla 1inh 3 aslx/lslx 1inh 6 asl/lsl 2ix1 5 asl/lsl 1ix 2 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3 ext 5 eor 3ix2 4 eor 2ix1 3 eor 1ix 8 9 5 brclr4 3dir 5 bclr4 2dir 3 bhcs 2rel 5 rol 2dir 3 rola 1inh 3 rolx 1inh 6 rol 2ix1 5 rol 1ix 2 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3 ext 5 adc 3ix2 4 adc 2ix1 3 adc 1ix 9 a 5 brset5 3dir 5 bset5 2dir 3 bpl 2rel 5 dec 2dir 3 deca 1inh 3 decx 1inh 6 dec 2ix1 5 dec 1ix 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3 ext 5 ora 3ix2 4 ora 2ix1 3 ora 1ix a b 5 brclr5 3dir 5 bclr5 2dir 3 bmi 2rel 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3 ext 5 add 3ix2 4 add 2ix1 3 add 1ix b c 5 brset6 3dir 5 bset6 2dir 3 bmc 2rel 5 inc 2dir 3 inca 1inh 3 incx 1inh 6 inc 2ix1 5 inc 1ix 2 rsp 1inh 2 jmp 2dir 3 jmp 3 ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix c d 5 brclr6 3dir 5 bclr6 2dir 3 bms 2rel 4 tst 2dir 3 tsta 1inh 3 tstx 1inh 5 tst 2ix1 4 tst 1ix 2 nop 1inh 6 bsr 2rel 5 jsr 2dir 6 jsr 3 ext 7 jsr 3ix2 6 jsr 2ix1 5 jsr 1ix d e 5 brset7 3dir 5 bset7 2dir 3 bil 2rel 2 stop 1inh 2 ldx 2imm 3 ldx 2dir 4 ldx 3 ext 5 ldx 3ix2 4 ldx 2ix1 3 ldx 1ix e f 5 brclr7 3dir 5 bclr7 2dir 3 bih 2rel 5 clr 2dir 3 clra 1inh 3 clrx 1inh 6 clr 2ix1 5 clr 1ix 2 wait 1inh 2 txa 1inh 4 stx 2dir 5 stx 3 ext 6 stx 3ix2 5 stx 2ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb
instruction set MC68HC05C9E advance information data sheet, rev. 0.1 82 freescale semiconductor
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 83 chapter 12 electrical specifications 12.1 maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note this device is not guaranteed to operate properly at the maximum ratings. refer to 12.5 dc electrical characteristics for guaranteed operating conditions. rating symbol value unit supply voltage v dd ?0.3 to +7.0 v input voltage normal operation self-check mode (irq pin only) v in v tst v ss ?0.3 to v dd + 0.3 v ss ?0.3 to 2 x v dd + 0.3 v current drain per pin (excluding v dd and v ss ) i25ma storage temperature range t stg ?65 to +150 c
electrical specifications MC68HC05C9E advance information data sheet, rev. 0.1 84 freescale semiconductor 12.2 operating temperature 12.3 thermal characteristics figure 12-1. test load characteristic symbol value unit operating temperature range MC68HC05C9Ep, fb MC68HC05C9Ecp, cfb t a ?40 to +105 c characteristic symbol value unit thermal resistance plas tic dual in-line (pdip) ja 60 c/w thermal resistance quad flat pack (qfp) ja 95 c/w v dd = 4.5 v pins r1 r2 c pa7?pa0 pb7?pb0 pc7?pc0 pd5?pd0, pd7 3.26 ? 2.38 ? 50 pf v dd = 3.0 v pins r1 r2 c pa7?pa0 pb7?pb0 pc7?pc0 pd5?pd0, pd7 10.91 ? 6.32 ? 50 pf v dd c r2 r1 test point see table see table see table
power considerations MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 85 12.4 power considerations the average chip-junction temperature, t j , in c, can be obtained from: t j = t a + (p d ja ) (1) where: t a = ambient temperature, c ja = package thermal resistance, junction to ambient, c/w p d = p int + p i/o p int = i dd v dd watts (chip internal power) p i/o = power dissipation on input and output pins (user determined) for most applications, p i/o ? p int and can be neglected. the following is an approximate relationship between p d and t j (neglecting p j ): p d = k (t j + 273 c) (2) solving equations (1) and (2) for k gives: k = p d (t a + 273 c) + ja (p d ) 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a .
electrical specifications MC68HC05C9E advance information data sheet, rev. 0.1 86 freescale semiconductor 12.5 dc electrical characteristics characteristic (1) (2) symbol min typ max unit output voltage i load = 10.0 a i load = ?10.0 a v ol v oh ? v dd ?0.1 ? ? 0.1 ? v output high voltage (i load = ?0.8 ma) pa7?pa0, pb7?pb0, pc6?pc0, tcmp, pd7, pd0 (i load = ?1.6 ma) pd5?pd1 (i load = ?5.0 ma) pc7 v oh v dd ?0.8 v dd ?0.8 v dd ?0.8 ? ? ? ? ? ? v output low voltage (i load = 1.6 ma) pa7?pa0, pb7?pb0, pc6?pc0, pd7, pd5?pd0, tcmp (i load = 10 ma) pc7 v ol ? ? ? ? 0.6 0.6 v input high voltage pa7?pa0, pb7?pb0, pc7?pc0, pd7, pd5?pd0, tcap, irq , reset , osc1 v ih 0.7 v dd ? v dd v input low voltage pa7?pa0, pb7?pb0, pc7?pc0, pd7, pd5?pd0, tcap, irq , reset , osc1 v il v ss ? 0.2 v dd v supply current (4.5?5.5 vdc @ f op = 2.1 mhz) run (3) wait (4) stop (5) 25 c ?40 to +105 c i dd ? ? ? ? 3.5 1.0 1.0 7.0 5.25 3.25 20.0 50.0 ma ma a a i/o ports hi-z leakage current pa7?pa0, pb7?pb0 (without pullup) pc7?pc0, pd7, pd5?pd0 i oz ?1.010 a input current reset , irq , osc1, tcap, pd7, pd5?pd0 i in ?0.5 1 a input pullup current (6) pb7?pb0 (with pullup) i in 5?60 a capacitance ports (as input or output) reset , irq , osc1, tcap, pd7, pd5, pd0 c out c in ? ? ? ? 12 8 pf 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 to +105 c, unless otherwise noted 2. typical values reflect measurements taken on average processed devices at the mi dpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ?0.2 v; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 4. wait i dd measured using external square wave clock source; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ?0.2 v; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2. wait i dd is affected linearly by the osc2 capacitance. 5. stop i dd measured with osc1 = 0.2 v; all i/o pins configured as inputs, port b = v dd , all other inputs v il = 0.2 v, v ih = v dd ?0.2 v 6. input pullup current measured with v il = 0.2 v
dc electrical characteristics MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 87 figure 12-2. maximum supply current versus internal clock frequency, v dd = 5.5 v figure 12-3. maximum supply current versus internal clock frequency, v dd = 3.6 v 1.00 ma 2.00 ma 3.00 ma 4.00 ma 5.00 ma 1.5 mhz 2.0 mhz 0.5 mhz 1.0 mhz internal clock frequency (xtal 2) supply current (i dd ) 50 ma stop i dd w a i t i d d r u n ( o p e r a t i n g ) i d d v dd = 5.5 v t = ?40 to 85 500 ma 1.00 ma 1.50 ma 0.5 mhz 1.0 mhz supply current (i dd ) w a i t i dd r u n ( op e r a t i n g) i d d v dd = 3.6 v t = ?40 to 85 stop i dd
electrical specifications MC68HC05C9E advance information data sheet, rev. 0.1 88 freescale semiconductor 12.6 control timing figure 12-4. tcap timing relationships characteristic (1) symbol min max unit frequency of operation crystal external clock f osc ? dc 2.1 2.1 mhz internal operating frequency (f osc 2) crystal external clock f op ? dc 2.1 2.1 mhz cycle time t cyc 480 ? ns crystal oscillator startup time t oxov ?100ms stop recovery startup time (crystal oscillator) t ilch ?100ms reset pulse width t rl 1.5 ? t cyc timer resolution (2) input capture pulse width input capture pulse period t resl t th , t tl t tltl 4.0 125 (3) ? ? ? t cyc ns t cyc interrupt pulse width low (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil (4) ?t cyc osc1 pulse width t oh , t ol 90 ? ns 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 to +105 c, unless otherwise noted 2. because a 2-bit prescaler in the time r must count four internal cycles (t cyc ), this is the limiting minimum factor in determining the timer resolution. 3. the minimum period t tltl should not be less than the number of cycle time s it takes to execute the capture interrupt service routine plus 24 t cyc . 4. the minimum t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 t cyc . t tltl (1) tcap pin t th (1) t tl (1) 1. refer to timer resolution data in 12.6 control timing .
control timing MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 89 figure 12-5. external interrupt timing figure 12-6. stop recovery timing diagram irq t ilih t ilil t ilih irq pin irq 1 irq n . . . a. edge-sensitive trigger condition . the minimum pulse width (t ilih ) is either 125 ns (f op = 2.1 mhz) or 250 ns (f op = 1 mhz). the period t ilil should not be less than the number of t cyc cycles it takes to execute the interrupt service routine plus 19 t cyc cycles. b. level-sensitive trigger condition . if after servicing an interrupt the irq remains low, (internal) normally used with wired-or connection the next interrupt is recognized. t ilih 4064 t cyc osc (1) t rl reset irq (2) irq (3) internal clock notes: 1. represents the internal clocking of the osc1 pin 2. irq pin edge-sensitive mask option 3. irq pin level- and edge-sensitive mask option 4. reset vector address shown for timing example reset or interrupt vector fetch $3ffe $3ffe $3ffe $3ffe $3ffe $3fff4
electrical specifications MC68HC05C9E advance information data sheet, rev. 0.1 90 freescale semiconductor figure 12-7. power-on reset timing diagram figure 12-8. external reset timing $3ffe 4064 t cyc v dd osc1 pin (2) internal clock (3) internal data bus (3) $3ffe $3ffe $3ffe $3ffe $3ffe $3fff note 1 1. power-on reset threshold is typically between 1 v and 2 v. 3. internal clock, internal address bus, and internal data bus are not available externally. new pch new pcl 2. osc1 line is meant to r epresent time only, not frequency. 4. reset outputs v ol during 4064 por cycles. notes: reset pin note 4 internal address bus (3) internal clock (1) internal address bus (1) notes: internal data bus (1) $3ffe $3ffe $3fff new pc 1. internal clock, internal address bus, and in ternal data bus are not available externally. 2. the next rising edge of the internal clock after the rising edge of reset initiates the reset sequence. new pch t rl new pcl op code reset (2) $3ffe $3ffe
serial peripheral interface timing MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 91 12.7 serial peripheral interface timing no. characteristic (1) symbol min max unit operating frequency master slave f op(m) f op(s) dc dc 0.5 2.1 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2.0 480 ? ? t cyc ns 2 enable lead time master slave t lead(m) t lead(s) note (2) 240 ? ? ns 3 enable lag time master slave t lag(m) t lag(s) note (2) 720 ? ? ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 340 190 ? ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 340 190 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 100 100 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 100 100 ? ? ns 8 slave access time (time to data active from high-impedance state) t a 0 120 ns 9 slave disable time (hold time to high-impedance state) t dis ? 240 ns 10 data valid master (before capture edge) slave (after enable edge) (3) t v(m) t v(s) 0.25 ? ? 240 t cyc(m) ns 11 data hold time (outputs) master (after capture edge) slave (after enable edge) t ho(m) t ho(s) 0.25 0 ? ? t cyc(m) ns 12 rise time (20% v dd to 70% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t rm t rs ? ? 100 2.0 ns s 13 fall time (70% v dd to 20% v dd , c l = 200 pf) spi outputs (sck, mosi, and miso) spi inputs (sck, mosi, miso, and ss ) t fm t fs ? ? 100 2.0 ns s 1. v dd = 5.0 vdc 10%; v ss = 0 vdc, t a = ?40 to +105 c, unless otherwise noted. refer to figure 12-9 and figure 12-10 for timing diagrams. 2. signal production depends on software. 3. assumes 200 pf load on all spi pins
electrical specifications MC68HC05C9E advance information data sheet, rev. 0.1 92 freescale semiconductor figure 12-9. spi master timing diagram note ss pin of master held high. msb in ss input sck (cpol = 0) output sck (cpol = 1) output miso input mosi output note 4 5 5 1 13 12 4 12 13 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 (ref) 13 11 10 12 11 (ref) 7 6 note ss pin of master held high. msb in ss input sck (cpol = 0) output sck (cpol = 1) output miso input mosi output note 4 5 5 1 13 12 4 13 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 (ref) 13 11 10 12 11 7 6 12 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) 12 note: this first clock edge is generated inte rnally, but is not seen at the sck pin. note: this last clock edge is generated internally, but is not seen at the sck pin.
serial peripheral interface timing MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 93 figure 12-10. spi slave timing diagram slave ss input sck (cpol = 0) input sck (cpol = 1) input miso input mosi output 4 5 5 1 13 12 4 13 msb in bits 6?1 8 6 10 11 11 12 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out slave ss input sck (cpol = 0) input sck (cpol = 1) input miso output mosi input 4 5 5 1 13 12 4 13 msb in bits 6?1 8 6 10 11 12 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave ti ming (cpha = 0) a) spi slave timing (cpha = 1) note: not defined but normally msb of character just received note: not defined but normally lsb of character previously transmitted
electrical specifications MC68HC05C9E advance information data sheet, rev. 0.1 94 freescale semiconductor
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 95 chapter 13 mechanical specifications 13.1 introduction this section describes the dimensi ons of the plastic dual in-line pack age (dip), and quad flat pack (qfp) mcu packages. package dimensions available at the time of th is publication are provided in this section. to make sure that you have the latest case outline specifications, contact one of the following: local freescale sales office world wide web at http://www.freescale.com follow world wide web on-line instructions to re trieve the current mechanical specifications. 13.2 40-pin plastic dual in-l ine (dip) package (case 711-03) figure 13-1. 40-pin plastic dip package (case 711-03) 120 40 21 b a c seating plane d f g h k n m j l dim min max min max inches millimeters a 51.69 52.45 2.035 2.065 b 13.72 14.22 0.540 0.560 c 3.94 5.08 0.155 0.200 d 0.36 0.56 0.014 0.022 f 1.02 1.52 0.040 0.060 g 2.54 bsc 0.100 bsc h 1.65 2.16 0.065 0.085 j 0.20 0.38 0.008 0.015 k 2.92 3.43 0.115 0.135 l 15.24 bsc 0.600 bsc m 1 n 0.51 1.02 0.020 0.040 notes: 1. position tolerance of leads (d), shall bewithin 0.25 (0.010) at maximum material conditions, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 1 0 0
mechanical specifications MC68HC05C9E advance information data sheet, rev. 0.1 96 freescale semiconductor 13.3 44-lead quad flat pack (qfp) (c ase 824a-01) figure 13-2. 44-lead qfp (case 824a-01)

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MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 97 chapter 14 ordering information 14.1 introduction this section contains ordering inform ation for the available package types. 14.2 mc order numbers table 14-1 shows the mc order numbers fo r the available package types. table 14-1. mc order numbers package type temperature range order number 40-pin plastic dual in-line package (dip) ?40 c to 105 c MC68HC05C9Ecp 44-pin quad flat pack (qfp) ?40 c to 105 c MC68HC05C9Ecfb 1. p = plastic dual in-line package (pdip) 2. fb = quad flat pack (qfp)
ordering information MC68HC05C9E advance information data sheet, rev. 0.1 98 freescale semiconductor
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 99 appendix a self-check mode a.1 introduction this appendix describes the self-check mode.self-check mode self-check mode is entered upon the rising edge of reset if the irq pin is at v tst and the tcap pin is at logic 1. a.2 self-check the self-check read-only memory (rom) at mask rom location $3f00?$3fef determines if the microcontroller unit (mcu) is functioning properly. these tests are performed: 1. input/output (i/o) ? functional test of ports a, b, and c 2. random-access memory (ram) ? counter test for each ram byte 3. timer ? test of counter register and ocf bit 4. serial communications interface (sci) ? transm ission test; checks for rdrf, tdre, tc, and fe flags 5. rom ? exclusive or with odd ones parity result 6. serial peripheral interface (spi) ? transmission test; checks for spif and wcol flags the self-check circuit is shown in figure a-1 .
self-check mode MC68HC05C9E advance information data sheet, rev. 0.1 100 freescale semiconductor figure a-1. self-check circuit schematic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 28 29 30 31 32 33 34 35 36 37 38 39 40 15 16 17 18 19 20 21 22 23 24 25 26 v dd 4.7 k ? reset irq pa5 pa4 pa3 pa2 pa1 pa0 pb0 pa6 pb1 pb2 nc pa7 pb3 pb4 pb5 pb6 pb7 v ss 20 pf 10 m ? 4 mhz 20 pf pc0 v dd osc1 osc2 tcap pd7 tcmp pd5/ss pd4/sck pd3/mosi pd2/miso pd1/tdo pd0/rdi pc1 pc2 pc3 pc4 pc5 pc6 pc7 v dd 1 m ? 10 v mc68hc05c9a mc34064 v dd v dd 10k cmos buffer (mc74hc125) 330 ? 330 ? 330 ? 330 ? notes: 1. v dd = 5.0 v 2. tcmp = nc v dd
self-check results MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 101 a.3 self-check results table a-1 shows the led codes that indicate self-check test results. perform these steps to activate the self-check tests: 1. apply 10 v (2 x v dd ) to the irq pin. 2. apply a logic 1 to the tcap pin. 3. apply a logic 0 to the reset pin. the self-check tests begin on the rising edge of the reset pin. reset must be held low for 4064 cycles after power-on reset (por), or for a time, t rl , for any other reset. for the value of t rl , see 12.7 serial peripheral interface timing and 12.6 control timing . table a-1. self-check circuit led codes pc3 pc2 pc1 pc0 remarks off on on off i/o failure off on off on ram failure off on off off timer failure off off on on sci failure off off on off rom failure off off off on spi failure flashing no failure all others device failure
self-check mode MC68HC05C9E advance information data sheet, rev. 0.1 102 freescale semiconductor
MC68HC05C9E advance information data sheet, rev. 0.1 freescale semiconductor 103 appendix b m68hc05cx family feature comparisons refer to table b-1 for a comparison of the features for all the m68hc05c family members.
MC68HC05C9E advance information data sheet, rev. 0.1 104 freescale semiconductor m68hc05cx family feature comparisons table b-1. m68hc05cx feature comparison c4 c4a 705c4a c8 c8a 705c8 705c8a c12 c12a c9 c9a/c9e 705c9 705c9a user rom 4160 4160 ? 7744 7744 ? ? 12,096 12,096 15,760?15,936 15,760?15,936 ? ? user eprom ? ? 4160 ? ? 7596?7740 7596?7740 ? ? ? ? 15,760?15,936 12,096?15,936 code security no yes yes no yes yes yes no yes no yes no yes ram 176 176 176 176 176 176?304 176?304 176 176 176?352 176?352 176?352 176?352 option register (irq/ram/ sec) no no $1fdf (irq/sec) no no $1fdf (irq/ram/ sec) $1fdf (irq/ram/sec) no no $3fdf (irq/ram) $3fdf (irq/ram) $3fdf (irq/ram) $3fdf (irq/ram) mask option register(s) no no $1ff0?$1ff1 no no no $1ff0?$1ff1 no no no no no $3ff0?$3ff1 portb keyscan (pullup/ interrupt) no yes mask option yes mor select- able no yes mask option no yes mor selectable yes mask option yes mask option no yes mask option no yes mor selectable pc7 drive standard high current high current standard high current standard high current high current high current standard high current standard high current port d pd7, 5?0 input only pd7, 5?0 input only pd7, 5?0 input only pd7, 5?0 input only pd7, 5?0 input only pd7, 5?0 input only pd7, 5?0 input only pd7, 5?0 input only pd7, 5?0 input only pd7, 5?0 bidirec- tional pd7, 5?0 bidirectional pd7, 5?0 bidirectional pd7, 5?0 bidirectional cop no yes yes no yes yes two types yes yes yes yes yes two types cop enable ? mask option mor ? mask option software software+ mor mask option mask option software software software software+ mor cop timeout ? 64 ms (@4 mhz osc) 64 ms (@4 mhz osc) ? 64 ms (@4 mhz osc) software selectable software+ mor selectable 64 ms (@4 mhz osc) 64 ms (@4mhz osc) software selectable software selectable software selectable software+ mor selectable cop clear ? clr $1ff0 clr $1ff0 ? clr $1ff0 write $55/$aa to $001d write $55/$aa to $001d or clr $1ff0 clr $3ff0 clr $3ff0 write $55/$aa to $001d write $55/$aa to $001d write $55/$aa to $001d write $55/$aa to $001d or clr $3ff0 clock monitor no no no no no yes yes no no yes yes yes yes (c9a mode) active reset no no no no no cop/clock monitor program- mable cop/clock monitor no no por/cop/ clock monitor por/cop/ clock monitor por/cop/ clock monitor por/c9a cop/ clock monitor stop disable no mask option no no mask option no no mask option mask option no no no mor selectable (c12a mode) notes: 1. the expanded ram map (from $30?$4f and $100?$15f) available on the ot p devices mc68hc705c8 and mc 68hc705c8a is not available on the rom devices mc68hc05c8 and mc68hc05c8a. 2. the programmable cop available on the mc68hc705c8 and mc68hc705c8a is not available on the mc68hc05c8a. for rom compatibility , use the non-programmable cop.
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